Cryptographic algorithms for communicating results from distributed electronic voting systems

Electronic voting systems are increasingly used in electoral processes ranging from specialized stand alone machines, up to complete paperless and remote voting system. Votes secrecy and confidence are necessary in any electoral process. Public or private key cryptographic systems can be used in LAN or WAN facilities. Low level cryptographic structures and basic algorithms are mentioned. Enhancement of security levels in distributed voting schemes, are shown based in concatenated operations before transmission. Finally, processing time reduction with specialized hardware and mixed cryptosystems are discussedVI Workshop de Procesamiento Distribuido y Paralelo (WPDP

AES development in FPGA

The National Institute of Standards and Technology (NIST) created a new standard known as Advanced Encryption Standard (AES), with the objective of developing the Federal Information Processing Standard (FIPS) which specifies an encryption algorithm capable of protecting sensitive information to be used by the government of the United States. In October 2000, the NIST selected Rijndael as the algorithm proposed for the AES.\nThe algorithm has a round shape made up by three uniform and non-reversible transformations which assures broadcast over the total set of fixed rounds and optimal non-linearity properties. This thesis presents an 8-bit FPGA implementation of the 128-bit block and 128 bit-key AES cipher.Reseña de la tesis presentada en 2006 por Mónica Cristina Liberatori para obtener el título de Magister en Redes de Datos (UNLP

High Performance VLSI Signal Processing: Innovative Architectures and Algorithms

The book intends to address the important aspects of high-performance signal processing with a focus on the recent development of VLSI technology for signal processing.\nThe editors collect much of all the research efforts and findings that have made high performance implementation of signal processing possible in the last decade in two volumes

Diseño y evaluación de arquitecturas de computadoras

In the first paragraph of the Introduction of the book the authors say The definition of computer architecture has generated many discussions since the emergence of what could be considered the first computer in 1943, the ENIAC . Later they add The main idea of all the proposals made in this direction is the same: define of computer components in different levels of study to produce a hierarchical description and to facilitate their understanding and design”. The authors' goal is to provide a textbook (written in Spanish) that systematically collect the most important techniques of design and evaluation of computer architectures

RTL fast convolution using the mersenne number transform

VHDL is a versatile high level language for the specification and simulation of hardware components. Here a functional VHDL model is presented for performing fast convolution based on Mersenne's number theoretic transform.\nFor filtering a rather long input sequence xn() we can decomposed it into a number of short segments, each of which can be processed individually. The output yn()then becomes a combination of partial convolutions. The superposition principle for linear operators is used here.\nEach partial convolution can be solved using the Discrete Fourier Transform (DFT) implementing a fast FFT (Fast Fourier Transform) algorithm. This DFT approach is the most popular.\nIn this paper we use the Mersenne Number Transform (MNT) as an alternative for the DFT in the framework of a register transfer level (RTL) implementation of the filter operation. Even when the MNT does not have a fast algorithm it can be see that RTL in the natural level of abstraction for the implementation of the MNT.\nThis work is conceived as part of an academic exercise in the use of VHDL for modeling a DSP algorithm all the way from the mathematical specification to the circuit implementation.Eje: Procesamiento distribuido y paralelo. Tratamiento de señale

Integración de bloques IP en diseños SoC

La metodología de diseño de sistemas SoC basándose en bloques IP (Hard o Soft) presenta diversos retos, desde las cuestiones relativas a la síntesis y validación de cada bloque IP, hasta las características de integración física y verificación funcional del sistema completo. Nos propusimos abordar la temática del diseño de bloques IP basándonos en descripciones de hardware por lenguaje (en particular VHDL) y avanzar en los mecanismos para re-utilizar dichos bloques como parte de distintos sistemas.Eje: Procesamiento Concurrente, Paralelo y Distribuid

A fast CORDIC co-processor architecture for digital signal processing applications

The coordinate rotational digital computer (CORDIC) is an arithmetic algorithm, which has been used for arithmetic units in the fast computing of elementary functions and for special purpose hardware in programmable logic devices. This paper describes a classification method that can be used for the possible applications of the algorithm and the architecture that is required for fast hardware computing of the algorithm.Área: Redes - Sistemas Operativos - Sistemas de Tiempo Real - Arquitectura de Procesadore

Una arquitectura para la transformada numérica de Mersenne

La convolución exacta de secuencias de números enteros es una de las operaciones más importantes del procesamiento digital de señales. Cuando se requiere exactitud no puede usarse el tradicional método de la DFT para acelerar el proceso de cálculo debido a los factores de peso trascendentes presentes en las transformadas de Fourier, La Transformada Numérica de Mersenne (MNT) es una alternativa a la aplicación directa de la convolución, que podría resultar en arquitecturas más simples (menos complejas) según se muestra en, En este trabajo se presenta un arquitectura simple que implementa la MNT, basada únicamente en registros de desplazamientos y sumadores en complemento a uno. Los registros de desplazamientos resuelven las multiplicaciones en forma cableada, representando así una complejidad de 0(1). Los sumadores complemento a uno son una variante carry look-ahead, los cuales presentan un retardo moderado y son fáciles de diseñar. La arquitectura aquí presentada ha sido descripta en VHDL y simulada

Diseño de bloques IP: programabilidad y re-utilización

Una metodología de diseño de sistemas SoC basada en bloques IP (Hard o Soft), requiere el estudio, análisis y proposición de soluciones a cuestiones tales como: comunicación inter-bloques IP, Software IP, validación de IP y del sistema, cambios tecnológicos y costo. Nos proponemos abordar estos temas en un primer paso como proveedores de bloques IP; para ello nos basaremos en descripciones de hardware por lenguaje (en particular VHDL).y evaluaremos reutilización y programabilidad de estos bloques.Eje: Redes, Arquitectura, Sistemas Distribuidos y Tiempo Rea

Towards a field configurable non-homogeneous multiprocessors architecture

Standard microprocessors are generally designed to deal efficiently with different types of tasks; their general purpose architecture can lead to misuse of resources, creating a large gap between the computational efficiency of microprocessors and custom silicon. The ever increasing complexity of Field Programmable Logic devices is driving the industry to look for innovative System on a Chip solutions; using programmable logic, the whole design can be tuned to the application requirements. In this paper, under the acronym MPOC (Multiprocessors On a Chip) we propose some applicable ideas on multiprocessing embedded configurable architectures, targeting System on a Programmable Chip (SOPC) cost-effective designs. Using heterogeneous medium or low performance soft-core processors instead of a single high performance processor, and some standardized communication schemes to link these multiple processors, the “best” core can be chosen for each subtask using a computational efficiency criteria, and therefore improving silicon usage. System-level design is also considered: models of tasks and links, parameterized soft-core processors, and the use of a standard HDL for system description can lead to automatic generation of the final design